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756 IP
351
0.118
UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library...
352
0.118
UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library...
353
0.118
UMC 55nm eFlash/LVT Logic Process 7-track ECO_M1 Generic cell library
UMC 55nm eFlash/LVT Logic Process 7-track ECO_M1 Generic cell library...
354
0.118
UMC 55nm eFlash/LVT Logic Process 7-track Genernic Core cell library
UMC 55nm eFlash/LVT Logic Process 7-track Genernic Core cell library...
355
0.118
UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library...
356
0.118
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...
357
0.118
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...
358
0.118
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...
359
0.118
UMC 55nm eFlash/RVT Logic Process 7-track ECO_M1 cell library
UMC 55nm eFlash/RVT Logic Process 7-track ECO_M1 cell library...
360
0.118
UMC 55nm eFlash/RVT Logic Process 7-track Genernic Core cell library
UMC 55nm eFlash/RVT Logic Process 7-track Genernic Core cell library...
361
0.118
UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library...
362
0.118
UMC 55nm eFlash/RVT Logic Process High Speed 12-track ECO_M1 cell library
UMC 55nm eFlash/RVT Logic Process High Speed 12-track ECO_M1 cell library...
363
0.118
UMC 55nm eFlash/RVT Logic Process High Speed 12-track Genernic Core cell library
UMC 55nm eFlash/RVT Logic Process High Speed 12-track Genernic Core cell library...
364
0.118
UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library
UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library...
365
0.118
UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library
UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library...
366
0.118
UMC 55nm eFlash/RVT LowK Logic Process 8-track Genernic Core cell Library
UMC 55nm eFlash/RVT LowK Logic Process 8-track Genernic Core cell Library...
367
0.118
UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library
UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library...
368
0.118
UMC 55nm LP/LVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm LP/LVT Logic Process MPCA cell library...
369
0.118
UMC 55nm LP/RVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm LP/RVT Logic Process MPCA cell library...
370
0.118
UMC 55nm LP/RVT LowK Logic Process 2.5VOD3.3V device RTC Core Library
UMC 55nm LP/RVT LowK Logic Process 2.5VOD3.3V device RTC Core Library...
371
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
372
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
373
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
374
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell....
375
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
376
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell....
377
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)...
378
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
379
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
380
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell...
381
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)...
382
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
383
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
384
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
385
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
386
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell....
387
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
388
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell...
389
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
390
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell....
391
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
392
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...
393
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
394
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....
395
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
396
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)...
397
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....
398
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
399
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
400
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
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